1. Field of the Invention
The present invention relates to drive (driver) circuits of outputting signals at high speed.
More particularly, the present invention relates to a low voltage differential signaling (LVDS) circuit.
2. Description of the Related Art
LVDS circuits intended for logical-signal output and high-impedance output at high speed are known. For example, Japanese Unexamined Patent Application Publication No. 2005-109897 discloses such an LVDS circuit.
FIG. 1 illustrates the basic circuit configuration of an LVDS circuit.
Referring to FIG. 1, an LVDS circuit 100 includes a first series circuit composed of a P-channel MOS transistor MP101 and an N-channel MOS transistor MN101, a second series circuit composed of a P-channel MOS transistor MP102 and an N-channel MOS transistor MN102, a first current source 11, and a second current source 12. The first series circuit is parallel to the second series circuit. The first current source 11 and the second current source 12 are connected to the first and second series circuits, respectively.
A first voltage VDD and a second voltage VSS are supplied to the LVDS circuit 100. A load circuit 110, equivalently represented as a resistor R, is connected to a node N1 and a node N2 in the LVDS circuit 100.
The operation of the LVDS circuit 100 in FIG. 1 will now be described in brief.
A control circuit (not shown) respectively supplies switching drive signals SW(φ1), SW(φ2), SW(φ3), and SW(φ4) to the transistors MP101, MP102, MN101, and MN102 so that two transistors diagonally arranged at opposite sides of the node N1, for example, the transistors MP101 and MN102 are simultaneously turned on or off in a first mode (phase) and the transistors MP102 and MN101 are simultaneously turned on or off in a second mode (phase) that is opposite in phase to the first mode.
The first and second switching drive signals SW(φ1) and SW(φ2) are differential signals (i.e., anti-phase signals or complementary signals). Similarly, the third and fourth switching drive signals SW(φ3) and SW(φ4) are differential (anti-phase) signals. On the other hand, the first and fourth switching drive signals SW(φ1) and SW(φ4) are in-phase signals. The second and third switching drive signals SW(φ2) and SW(φ3) are also in-phase signals.
In other words, in the first mode, the diagonally opposing transistors MP101 and MN102 are simultaneously turned on and the diagonally opposing transistors MP102 and MN101 are turned off. Consequently, the first current source 11, the transistor MP101, the node N1, the load circuit 110, the node N2, the transistor MN102, and the second current source 12 constitute a circuit, thus providing a current path P2 shown by a dashed line.
On the other hand, in the second mode, the diagonally opposing transistors MP102 and MN101 are simultaneously turned on and the diagonally opposing transistors MP101 and MN102 are turned off. Consequently, the first current source 11, the transistor MP102, the node N2, the load circuit 110, the node N1, the transistor MN101, and the second current source 12 constitute a circuit, thus providing a current path P1 shown by a solid line.
Repeating the above-described operation permits an output current Iout, of which the polarity is switched between positive and negative, to flow through the load circuit 110.
Japanese Unexamined Patent Application Publication No. 2005-109897 discloses a technique for providing a bypass circuit to overcome disadvantages of the above-described LVDS circuit.
The disadvantages of the above-described LVDS circuit will now be described.
In the LVDS circuit 100, the transistors MP101 and MN102 each function as an analog switch that allows the output current Iout to flow through the load circuit 110 upon providing the above-described current path P2 and the other transistors MP102 and MN101 each operate as an analog switch that allows the output current Iout to flow through the load circuit 110 upon providing the current path P1. In each of the transistors MP101, MP102, MN101, and MN102 operating as analog switches, a voltage drop is caused by the on-resistance of the transistor. The operating voltage of the LVDS circuit 100 is expressed by the following Expression (1):[VdsP+(Ron1+Ron2+R)×Iout÷VdsN]<(VDD−VSS)  (1)where VdsP denotes the pinch-off voltage of the P-channel transistor, VdsN indicates that of the N-channel transistor, and Ron1 and Ron2 denote the respective on-resistances.
Unfortunately, it is difficult to reduce the difference (VDD−VSS) between the first voltage VDD and the second voltage VSS.
When the second voltage VSS is set to the ground potential, it is difficult in the LVDS circuit 100 to lower the first voltage VDD. Disadvantageously, it is difficult to realize the low-voltage operation of the LVDS circuit. Therefore, the size of each transistor is increased. For example, when the LVDS circuit 100 is constructed as an IC, it is difficult to reduce the layout area of the circuit.
In order to reduce the on-resistance of each transistor, the size of the transistor may be increased. On the other hand, in order to allow the LVDS circuit to operate at high speed, the gate of each transistor should be driven at high speed. The larger the size of each transistor, the larger the gate capacitance. Disadvantageously, it results in an increase in the power consumption of logic elements.
Japanese Unexamined Patent Application Publication No. 2004-112453 discloses a circuit which includes a first differential amplifier 21 and a second differential amplifier 22, as shown in FIG. 2, in order to overcome the above-described disadvantages.
Referring to FIG. 2, a first switching drive signal SW(φ1) and a second switching drive signal SW(φ2), which are supplied to the first differential amplifier 21, are differential (anti-phase) signals. Similarly, a third switching drive signal SW(φ3) and a fourth switching drive signal SW(φ4), which are supplied to the second differential amplifier 22, are differential (anti-phase) signals.
The operating voltage of an LVDS circuit 100A illustrated in FIG. 2 is expressed as the following Expression (2).(VdsP+VdsN)<(VDD−VSS)  (2)
As is clear from Expression (2), the LVDS circuit 100A has advantages in that the circuit is not affected by the on-resistances of transistors and the operating voltage of the circuit is reduced.